Planarizing semiconductor wafers during manufacture is generally known in the art. Chemical mechanical polishing (CMP) is generally known in the art and a currently preferred method to planarize semiconductor wafers during manufacture. For example U.S. Pat. No. 5,177,908 issued to Tuttle in 1993 describes a finishing element for semiconductor wafers, having a face shaped to provide a constant, or nearly constant, surface contact rate to a workpiece such as a semiconductor wafer in order to effect improved planarity of the workpiece. U.S. Pat. No. 5,234,867 issued to Schultz et al. in 1993 describes an apparatus for planarizing semiconductor wafers which in a preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer where a motor for rotating the platen and a non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. Other planarizing process for adding to or removing material to form a planar surface are generally known. Electrochemical planarizing and vapor deposition processes (such as electroplating, electropolishing, Chemical Vapor Deposition (CVD) and/or Physical Vapor Deposition processes) processes are generally known to those skilled in the semiconductor wafer processing arts.
Semiconductor wafer fabrication generally requires the formation of layers of material having particularly small thicknesses. A typical conductor layer, such as a metallization layer, is generally 2,000 to 6,000 angstroms thick and a typical insulating layer, for example an oxide layer, is generally 3,000 to 5,000 angstroms thick. The actual thickness is at least partially dependent on the function of the layer along with the function and design of the semiconductor wafer. A gate oxide layer can be less than 100 angstroms thick while a field oxide is in the thousands of angstroms in thickness. In higher density and higher value semiconductor wafers the layers can be below 500 angstroms in thickness. Generally during semiconductor fabrication, layers thicker than necessary are formed and then thinned down to the required tolerances with techniques needed such as Chemical Mechanical Polishing. Because of the strict tolerances, extreme care is given to attaining the required thinned down tolerances. As such, it is generally useful to accurately control the thinning of the layer during the thinning process and also as it reaches the required tolerances. The end point for the thinning, planarizing, or polishing operation has generally very close tolerances. One current method to remove selected amounts of material is to remove the semiconductor wafer periodically from the planarizing and/or polishing for measurements such as thickness layer measurements. Although this can be done it is time consuming and adds extra expense to the operation. Further the expensive workpieces can be damaged during transfer to or from the measurement process further decreasing process yields and increasing costs. In fact, microscratches which are deep enough to penetrate the target surface can occur before the target surface depth is reached causing lower yields and lost product. Microscratches and other unwanted surface defects formed during the planarizing and/or polishing can adversely lower the polishing yield adding unnecessary expense to the polishing step in semiconductor wafer manufacture.